It is known that for some applications it is preferable to use single polysilicon level EPROM cells (that is, with the floating gate coupled capacitatively to doped source and drain regions of a semiconductor substrate and to a control gate also constituted by a doped region of the same substrate) rather than the more traditional twin polysilicon level EPROM cells.
The custom is also known of accomplishing simultaneously with the cells of an EPROM memory matrix the transistors of an external circuit.
When very small transistors are needed, these can be accomplished with either the LDD (light doped drain) or the DDD (double doped drain) technology, that is, with the formation, on both sides of the floating gate, of oxide spacers superimposed over lightly doped substrate regions adjacent to highly doped source and drain regions.
In this way it is possible to reduce the problems of aging of traditional transistors, while still maintaining the electrical continuity necessary for the transistor's correct operation.
This technology is not applicable to EPROM cells, because the presence of such lightly doped regions would make the writing process extremely slow.
For a normally-fast writing process it is indeed necessary for the EPROM cells to have their floating gate partially superimposed over highly doped source and drain regions.
In order to accomplish a matrix of traditional single polysilicon level EPROM cells simultaneously with LDD- or DDD-type external circuit transistors it is, on the other hand, necessary to use an additional mask with a consequent increase in time and costs.